One of the biggest challenges facing PCB designers is not understanding the cost drivers in the PCB manufacturing process. This article is the latest in a series that will discuss these cost drivers (from the PCB manufacturer’s perspective) and the design decisions that will impact product reliability.
Design for manufacturing (DFM) is defined as the practice of designing printed circuit boards that meet not only the capabilities of the customer’s assembly manufacturing process, but also the capabilities of the board fabrication process at the lowest possible cost. While not a substitute to early design engagement with the PCB fabricator, this series of articles will provide guidelines that will help to “design for success.”
PCBs that contain controlled impedance lines require specific constructions and tighter manufacturing process controls. The fabricator needs to tailor the construction for PCBs requiring impedance to precisely match the required nominal impedance values. The fabrication drawing should specify the required nominal impedance and tolerance and the fabricator will create a construction to meet the intended design impedance requirements.
Primary Impedance Factors
- Trace width
- Copper thickness
- Dielectric spacing
- Indicated “Reference Only.” See Impedance Requirements
- Overall PCB thickness
- Material requirements
Top fabricators use some form of impedance modeling software to determine the specific PCB construction required to produce the specified impedance. The PCB drawing should only specify the nominal impedance, tolerance, and nominal line width. This will allow for the creation of the most cost-effective PCB material construction.
Multiple Impedance Considerations
Some PCBs require multiple impedance values on the same signal layers. It is critical that your PCB fabricator can create impedance coupons to reflect the appropriate model for each impedance requirement. However, testing multiple impedance values on a given signal layer will cause the coupon to be wider than normal. These wider coupons take up additional valuable panel real estate, and because of this, designate one target impedance value to be tested per layer whenever possible.
There are two types of impedance classifications that are generally specified: single-ended and differential.
Single-ended impedance is established by the interaction of a single trace and its reference plane(s). There are four basic impedance classifications:
- Microstrip: A trace on an outer layer with a single reference plane below it.
- Embedded microstrip: A microstrip line that has a dielectric over the top of it; solder mask will change a microstrip into an embedded microstrip line.
- Stripline: A trace on an internal layer that has a reference plane above and below it.
- Dual stripline or offset stripline: A stripline which is offset between the two reference planes; it generally is used when two adjacent signal layers are routed orthogonally and have reference planes outside of them.
Differential impedance is established by the interaction of two traces and their reference plane(s). There are five basic impedance classifications:
- Edge coupled microstrip: Comprised of two adjacent traces on an outer layer with a single reference plane below it.
- Edge coupled embedded microstrip: An edge coupled microstrip line that has a dielectric over the top of it; solder mask will change a microstrip into an embedded microstrip line.
- Edge coupled stripline: A configuration with two adjacent traces on an internal layer, which is centered between a reference plane above and below it.
- Edge coupled dual stripline or offset stripline: An edge-coupled stripline which is offset between the two reference planes; it is generally used when two adjacent signal layers are routed orthogonally and have reference planes outside of them.
- Broadside coupled stripline: A configuration with the two differential lines on adjacent layers directly one above the other; these are offset striplines centered between their two reference planes.
Controlled Impedance Design Guidelines
- Standard impedance tolerance: ±10%
- Tighter tolerances are available but need special care
- Broadside-coupled striplines should ideally be used on a core
- Try to avoid having prepreg between then. This is required to control the Z-axis alignment between the two signal layers
- Specify the design trace-to-trace spacing for correct modeling
- Give the impedance lines a different aperture (usually 0.0001” difference) than non-impedance traces
- Makes it easier to adjust line widths if needed
- Specify reference planes
Minimizing Impedance Costs
Using the following guidelines will help to minimize impedance costs:
- Specify impedance only on layers that really require this
- Route all controlled impedance traces onto the same layer
- Specify a ±10% tolerance when possible
- Designate one target impedance value to be tested per layer
- Couple power/ground on adjacent layers when possible
- Allow for modifying the construction to meet overall tolerance
All impedance coupons are 100% tested when specified by the customer. After comparisons against specified values, the measurements are electronically stored.
Serialization is a traceability process for controlled impedance jobs. Impedance is typically measured with a TDR (time domain reflectometer) by adding test coupons to the panel. Before the impedance has been tested, the coupon and PCB have a serial number marked on them.
Understanding the cost drivers in PCB fabrication and early engagement between the designer and the fabricator are crucial elements that lead to cost-effective design success. Following your fabricator’s DFM guidelines is the first place to start.
This article is part of Anaya Vardya’s series “DFM-101”. It originally appeared in the July 2021 issue of Design007 Magazine.